1. Field of the Invention
The present invention relates to electrically interconnecting via structures and methods of making same in material, such as, semiconductor material. More particularly, the present invention relates to conductive through via structures and processes for making same in electronic device lo structures, such as in semiconductor wafers, semiconductor chips, components and the like, and in electronic device carriers for such semiconductor wafers, chips, components, and the like.
2. Background and Related Art In the packaging of electronic devices, such as, semiconductor chips or wafers, device carriers may be used to interconnect the devices. Where electronic devices are connected to another level of packaging, the carriers typically require conductive vias extending through the carrier to connect the devices to the next level of packaging.
Electronic device carriers may be fabricated from a variety of different materials, such as, glass, ceramic, organic and semiconductor materials or combinations of these and other materials in single or multiple layers.
Electronic device carriers made of semiconductor material, such as, silicon, offer a number of advantages in packaging, such as, ease of manufacturing and reliability and high connection density One of the challenges with this technology is the requirement for complex processing to be carried out on the backside of the wafer. Conventional complex processing steps involving lithography, RIE etching and the like may become much more difficult and costly when carried out on the backside of a semiconductor carrier, such as, silicon.
One prior art approach to creating conductive vias in semiconductor carriers, such as silicon, use what might be called a “via first” approach. The general steps in such an approach are etching the vias, forming insulation layers on the via walls and metallization. When a “blind via” approach is used, the vias are not etched through the wafer layer so that a “through via” is rendered only after the carrier is suitably thinned to expose the via bottoms. An example of such an approach may be seen in U.S. Pat. No. 5,998,292.
There are, however, a number of difficulties with this type of approach. For example, one difficulty is controlling vertical structure dimensions. Another difficulty is controlling the backside thinning depth stop and isolation of the process steps.
Some approaches to creating through vias in semiconductor carriers may require backside lithographic processing and etching steps. Such processing on the backside of a silicon carrier, adds to processing complexity. As an example, U.S. application Ser. No. 11/214,602 filed Aug. 30, 2005, and assigned to the assignee of the present invention, uses photolithography and RIE processing steps on the backside of a silicon wafer in forming through vias in the wafer.